1. Field of the Invention
The present invention relates to a method for processing data in a communication system and, more particularly, to a method for performing turbo decoding in a mobile communication system.
2. Background of the Related Art
As known in the related art, a turbo code generator includes two or more recursive systematic convolutional (RSC) encoders arranged in parallel through an interleaver Turbo codes generated through the turbo code generator are used to transmit data at high transmission rate in the standard for an advanced mobile communication system.
The turbo codes are processed for generating bit rows in a block unit. Particularly, in the case where large sized data bit rows are encoded, the turbo codes have excellent coding gain to convolutional codes. The turbo codes are iteratively decoded on codes of a simple component in a receiving system, so that the receiving system has excellent error correction capability.
Recently, a method for simply performing turbo decoding and a turbo decoder have been suggested to support data transmission at high speed under the mobile communication environment. According to the turbo decoder, input code words pass through two convolutional decoders in turn. Therefore, the turbo decoder has a simplified structure.
However, in order that the input code words iteratively pass through two convolutional decoders, the two convolutional decoders should have output values corresponding to soft decision values having a probability rate of “0” or “1,” not hard decision values such as “0” or “1.” To obtain such soft decision values, a Maximum A Posteriori (MAP) decoding method has been suggested, in which a posteriori probability value of a data bit is calculated and the data bit is decoded to obtain the maximum posteriori probability value.
FIG. 1 illustrates a structure of a related art turbo decoder. The related art turbo decoder includes a first MAP decoder D1 101 and a second MAP decoder D2 103 corresponding to each RSC encoder of an encoder. The turbo decoder further includes an interleaver 102 that serves to perform the same function as that of an interleaver of the encoder, first and second deinterleavers 104 and 105 having an inverse function to that of the interleaver 102, and first to third delay circuits 107 to 109 for delaying signal processing while the first MAP decoder 101 and the second MAP decoder 103 perform their respective logic operations.
The operation of the related art turbo decoder will be described. The code words input to the turbo decoder are decoded by passing through the two MAP decoders 101 and 103. Particularly, the turbo decoder does not decode the successively input code words at one time but decodes them by passing them through the two MAP decoders. As the iterative number of passes through the two MAP decoders 101 and 103 increases, decoding performance is improved.
As shown in FIG. 1, the first MAP decoder 101 decodes composite signals of systematic symbols xk, parity symbols yk, and extrinsic information dk having (N−1)th iterative number of times among iterative decoding number of times. The second MAP decoder 103 decodes an output signal of the interleaver 102 and parity symbols yk. An input signal of the interleaver 102 is a composite signal of the output signal from the first MAP decoder 101 and the extrinsic information signal dk, having (N−1)th iterative number of times. The extrinsic information signal is delayed by the first delay circuit 107 for a certain time.
First deinterleaver 104 deinterleaves a composite signal of the output signal of the interleaver, which passed through the second delay circuit 108, and the output signal of the second MAP decoder 103. First deinterleaver 104 outputs the extrinsic information signal dk having Nth iterative number of times. Second deinterleaver 105 deinterleaves a limited signal of the output signal of the second MAP decoder 103 and outputs the deinterleaved signal as a final output bit of the turbo decoder.
FIG. 2 is a diagram illustrating the operation of the related art turbo decoder. Output signals of the first MAP decoder 101 and the second MAP decoder 103 are called extrinsic information. As shown in FIG. 1, the extrinsic information output from the first MAP decoder 101 is interleaved and then used as the input signal of the second MAP decoder 103. The output signal of the second MAP decoder 103 is deinterleaved and then used as the input signal of the first MAP decoder 101.
In other words, once decoding of the first MAP decoder 101 is completed (S10), interleaving is performed on the decoded signal (S11). Once decoding of the second MAP decoder 103 is completed (S12), deinterleaving is performed on the decoded signal (S13). Decoding with the second MAP decoder 103 begins after the completion of the interleaving.
As described above, in the related art turbo decoding, the MAP decoding operation, the interleaving operation, and the deinterleaving operation are sequentially performed. Accordingly, a problem arises in that the decoding time becomes longer. Also, to sequentially perform the above operations, the input and output signals of the interleaver 102 should be stored. To this end, as shown in FIG. 1, a memory 106 that can store two sets of extrinsic information is required. Memory 106 may be used to store the input and output signals of the first and second deinterleavers 104 and 105.
According to the 3GPP WCDMA specification, since the size of the turbo code block is maximum 5114 bit, a memory having a bit capacity of 5114*n*2 is required, wherein n is a positive integer, which is the number of bits of the extrinsic information, and is generally between 4 bits and 8 bits.
The above reference is incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.